The present invention relates to digital frequency counting systems. More particularly, the invention pertains to continuous counting systems useful for deriving the frequency of an input signal.
As used herein, the term continuous counting system refers to a system arranged for counting the cycles of an input signal occurring during each of a plurality of temporally adjacent timing intervals of predetermined duration for deriving the frequency of the input signal. In such a system, the count accumulated by the counter during each timing interval is related to the frequency of the input signal by the expression f=N/d, where f is the input signal frequency, N is the accumulated count and d is the time duration of the timing interval. By way of example, assuming an accumulated count of 664 during a 16.6 ms timing interval, it will be observed that the input signal is characterized by a frequency of 40 KHz.
In order to accumulate counts accurately representing the frequency of an input signal, continuous counting systems of the foregoing type conventionally include means for suitably resetting a binary counter at the initiation of each timing interval. In other words, the count accumulated during each timing interval must be independently derived and account for each cycle of the input signal occurring during the interval. For this purpose, clock circuits of various configuration are normally used to develop reset pulses for resetting the counter to state 0 at the beginning of each timing interval. Particularly in binary counters of the type which count by sensing logical transitions of the input signal, it is important that the reset pulses be relatively narrow compared to the period of the input signal in order that a pertinent logical transition not be inadvertently skipped. On the other hand, device responsiveness characteristics dictate that the reset pulses must be of some minimum width in order to confidently reset the counter. For relatively low speed logic families, such as CMOS and I.sup.2 L, reset pulses on the order of 0.5 microseconds are typically used whereas higher speed logic families such as TTL require reset pulses of only about 0.1 microseconds. Of course, the more narrow reset pulses provide increased confidence in the integrity of the accumulated count.
Prior art techniques for achieving narrow reset pulses commonly employ various types of circuits for differentiating a timing reference signal. Traditionally, analog RC circuits have been used for this purpose although recently digital differentiators have become popular. Typically, a digital differentiator comprises a string of series connected inverters coupling the timing reference signal to one input of a suitable logic gate, the other input of the gate being coupled directly to the source of the reference signal. The narrow reset pulses are obtained at the output of the gate and have pulse widths defined by the signal propagation delay time introduced by the series connected inverters.
In either case, i.e. analog or digital differentiators, component fabrication inconsistencies or variations result in a situation where it is quite difficult to repeatably provide differentiators which consistently develop output reset pulses of predictably narrow pulse width, thereby degrading counting accuracy. This lack of predictability, to a large extent, is caused by the tolerances associated with the resistive and the capacitive components in analog differentiators and by the extreme difficulty of precisely duplicating inverter characteristics in digital systems. The present invention seeks to overcome the foregoing problems by developing output pulses independently of differentiating circuits for suitably presetting the counter at the initiation of each counting interval.